A prior art transistor logic tristate device with reduced output capacitance described in U.S. Pat. No. 4,311,927 is illustrated in FIG. 1. The tristate output device is provided with an input E for receiving binary data signals V.sub.i of high and low potential and for transmitting output signals V.sub.o to a common bus, not shown, coupled at the output B. For operation in the bistate mode, the output device includes a pull-up transistor element comprising Darlington transistor pair Q2 and Q3 for sourcing current to the output B from high potential V.sub.cc, a pull-down transistor element Q4 for sinking current from the output B to low potential or ground, and a phase splitter transistor element Q1 coupled at the input E to control the states of the pull-up and pull-down transistor elements in response to data signals V.sub.i at the input. The pull-down transistor element Q4 includes a conventional squaring network at its base comprised of resistor R3 and R4 and transistor Q5.
For the tristate mode of operation an enable gate, not shown, is operatively coupled at A to establish a high impedance third state at the output B of the device when the enable gate is at low potential. For reducing the effective output capacitance during the high impedance third state, an active discharge sequence comprising transistors Q8, Q7, and Q6 is operatively coupled between the base of the pull-down transistor element Q4 and the enable gate at A. The active discharge sequence affords a low impedance route to ground from the base of the pull-down element through transistor Q8 when the enable gate maintains a low potential at A and the output device is in the high impedance third state. As a result, low to high potential transitions on a common bus coupled at the output B of the device will not incidentally drive the pull-down transistor element Q4 to conduction because any capacitive Miller feedback current through the collector to base capacitance of Q4 is rapidly diverted and discharged to ground.
On the other hand the active discharge sequence affords a high impedance to current flow in the opposite direction toward the base of the pull-down transistor element Q4 when the enable gate maintains a high potential at A for operation of the output device in the bistate mode. Thus, during the bistate mode of operation the active discharge sequence blocks current flow from any high potential current source coupled to the enable gate.
The active discharge sequence as described in U.S. Pat. No. 4,311,927 comprises a sequence of three active elements, Q8, Q7, and Q6, in a double inversion series coupling between the enable gate at A and the base of pull-down transistor element Q4. The collector potential of Q6 follows in phase with the enable gate potential maintained at A, the collector potential of Q7 is out of phase with the enable gate potential and the collector potential of Q8 again follows in phase the enable gate potential at A. As a result, when the enable gate is at low potential and the output device is in the high impedance third state, the collector of active discharge transistor element Q8 is also at low potential because Q8 is conducting providing a route to ground from the base of pull-down transistor Q4 for diverting capacitive feedback Miller current to ground. The large capacitance that would otherwise effectively be seen at the output is therefore eliminated. When the enable gate maintains high potential at A, the collector of Q8 is also at high potential because Q8 is nonconducting presenting a high impedance to current flow in the direction of the base of the pull-down transistor element.
The active discharge sequence of three active transistor elements, Q8, Q7, and Q6, coupled between the enable gate at A and the base of transistor Q4 is abstracted from the overall output device and shown as a subcircuit in FIG. 2. The base drive for transistor Q6 and the collector current for transistor Q7 are derived from the potential source V.sub.cc through the separate base resistor R6 and collector resistor R7 respectively.
Further description of the transistor logic tristate device with reduced output capacitance illustrated in FIGS. 1 and 2 and the function of particular components is further developed in the U.S. Pat. No. 4,311,927 referred to above.